Phase-locked loops (PLL) find many applications. Among them is their use for recovering a clock signal out of a data signal stream. FIG. 1 shows a phase-locked loop (PLL) 110. In PLL 110, data 114 is coupled to a pulse gate circuit 120 also known as a pulse removing circuit. The pulse gate circuit 120 is connected to a phase-frequency detector 118. The phase-frequency detector 118 is coupled to a charge pump 122, which in turn is coupled to a loop filter 126. The loop filter is coupled to a voltage controlled oscillator (VCO) 130. A feedback link 146 connects the output of the VCO 130 to the phase-frequency detector 118, as shown in FIG. 1. The VCO 130 has an output 134 for coupling a recovered clock signal 136 to a memory 138. The data 114 also is coupled directly to the memory 138 via data link 142. The recovered clock signal 136 clocks data 114 into memory 138.
A typical application of the PLL 110 may be in a hard disk drive system. In the standard hard disk drive system, data needs to be sent from a disk drive 150 to memory 138 of, for example, a microprocessor. An example of data sent from disk drive 150 is servo data. Servo data contains positioning information of a head of a disk drive 150 with respect to the disk of the disk drive 150.
Clock signal information associated with data 114 is embedded in the data signal 114. In fact, such clock information may be available from voltage transitions of the data signal 114. Transmitting clock information along with the data 114 on data signal link 154 obviates the need for an extra link for the clock signal. Sometimes, an extra link is not even available, as in the case of a serial link, such as an RS-232 (Recommended Standard-232) link. RS-232 is a standard for serial transmission between computers and peripheral devices. Whether data is sent over serial or parallel data channels, in synchronous systems, clock information is needed for receiving the data. So embedded clock signal information has to be recovered from the data 114. This clock recovery is performed by PLL 110. PLL 110 frequency and phase locks onto the embedded clock signal information.
To minimize frequency and phase errors between the actual clock signal and the recovered clock signal 136, the recovered clock signal 136 is fed back via feedback link 146 to the pulse gate circuit 120. The pulse gate circuit 120 passes through a VCO pulse every time it receives a pulse on data signal link 154. The pulse gate circuit 120 transmits the recovered clock signal 136 to the phase-frequency detector 118. The phase-frequency detector 118 minimizes phase and frequency differences between the clock signal associated with data 114 and the recovered clock signal 136. When the PLL 110 is in a locked state, then the phase and frequency error between the recovered clock signal 136 and the clock signal in the data 114 is very small or zero.
The PLL 110 can lose lock. Loss of lock is the state of the PLL when the phase and frequency differences between the recovered clock signal 136 and the clock of the data signal 114 have become substantial. A loss of lock of PLL 110 can occur, for instance, when, in a particular data transmission format, data signal logic ones are transmitted as low to high to low voltage transitions, whereas logic zeros are represented by no transitions. So, when there is an extended series of logic zeros being transmitted, the PLL 110 is likely to lose lock, because an indication of the clock signal in data signal 114 is unavailable for that time.
Once lock is lost, the frequency of the signal at output 134 of VCO 130 drifts away from the clock of data signal 114. Depending on the particular output frequency range capability of the VCO 130, the frequency of the signal at the output 134 of the VCO 130 can drift significantly far away from the clock of data signal 114. Consequently, once data signal 114 again includes logic ones, i.e., low to high to low voltage transitions, PLL 110 will have to reacquire lock. Such reacquisition requires time and can significantly slow the transfer of data 114 from disk drive 150 to memory 138. The further away the frequency of the signal at the output 134 can drift from the clock associated with data signal 114, the more time the PLL 110 will need to reacquire lock.
To minimize the time required for reacquiring lock, PLLs 110 are designed with VCOs 130 that have a narrow output frequency range centered on the expected frequency, i.e., center frequency, of the clock associated with data 114. Usually, the frequency at which data 114 is clocked is known. However, a problem associated with the narrow output frequency range approach is that VCOs 130 may have considerably varying center frequencies. The center frequency of the VCO 130 can vary by as much as 100 percent. So, for instance, for a desired VCO output frequency of 50 MHz (mega-hertz), the actual center frequency may be 100 MHz. These variations are due to VCO manufacturing process tolerances. As a result, some VCOs 130 may be unable to provide a recovered clock signal 136 at the clock frequency of data 114.
To overcome the problem of the output frequency range of the VCO 130 possibly being outside that of the clock of data signal 114, VCO 130 can be tuned for operation over the desired frequency range. This tuning can involve trimming of components of the VCO 130, such as, for instance, switching in or out certain components, like resistors.
To avoid the need for tuning VCO 130, an alternative approach to minimizing time for reacquiring lock of PLL 110, is to manufacture VCO 130 with a relatively wide frequency range, such that none of the process variations will remove the output frequency range of the VCO 130 from coverage of the clock frequency of data 114.
But, as discussed above, widening of the range of output frequency range of the VCO 130, permits VCO 130 to drift further away from the clock frequency of the data 114 than a VCO 130 could that has a relatively narrow output frequency range. To minimize the lock reacquisition time of PLL 110, a master PLL can be used to keep VCO 130 at the frequency of the clock of data 114 during periods when PLL 110 has lost lock. In this arrangement, the PLL 110 of FIG. 1 becomes a slave PLL. The VCO 130 of this slave PLL 110 is controlled by the master PLL.
The approaches discussed above, while feasible, are costly in terms of testing time and silicon area. The VCO 130 with a narrow output frequency range requires trimming of VCO components and testing to assure that it has been trimmed appropriately. Furthermore, in the system that includes the master PLL, additional silicon area on a chip has to be made available for this master PLL.